The present invention relates to testing of memory blocks of an integrated circuit, in general, and, more particularly, to a system and method of testing a plurality of memory blocks of an integrated circuit in parallel using a data word comparator of latching bit registers disposed on the integrated circuit for each memory block thereof.
Memory blocks of a very large scale integrated (VLSI) circuit or chip are generally tested by an off-chip tester programmed to control each memory block under test to perform writes and reads of data, and to perform compares of such data for memory block validation and integrity verification. Memory block testing generally comprises writing test data into registers or rows of the memory block and reading the resultant data therefrom. Performance of the write and read test functions require address, control, read data and write data signal lines which are referred to as input/output (I/O) tester channels. Such I/O tester channel signal lines are brought out to pins of the chip for connecting to the off-chip tester. Once connected, the tester may write test data words into the registers or rows of the memory block under test by placing addresses and test data on the address and write data channels, and issuing write commands. Likewise, the tester may read resultant data words from the registers or rows by issuing a read command and accessing the data over the read data channel for analysis. Generally, the tester is programmed to perform comparisons of the write and read data of each of the registers of a memory block and store and analyze the results.
Typically, many of the on-chip memory blocks are identical, like tag memories in an associative cache, for example. Accordingly, an identical test may be run on each such memory block. For such chips having multiple memory blocks, the test designer has to make a trade off decision between testing the multiple memory blocks sequentially or in parallel. Testing the memory blocks of a chip in parallel requires a large amount of I/O bandwidth support, i.e. a large number of I/O tester channels. Testing the individual memory blocks of a chip sequentially increases the amount of test time.